General Comments on Alignment Marks
Proper alignment marks are critical to maintaining overlay accuracy throughout a process flow. This may require careful planning and consideration of the entire process before the marks are written. Alignment can be compromised very easily if proper consideration is not taken. This can needlessly waste valuable time and resources. Please feel free to contact any of the EBL staff members if you have questions regarding alignment or any other ebeam issues.
JEOL Alignment Mark Strategy
The JEOL systems use alignment marks to establish a coordinate system to expose patterns aligned with a previously exposed pattern. The placement accuracy of these patterns depends on the accuracy of the tool used to create the alignment marks. The most accurate alignment will always be “tool to itself”. This means that to achieve the best alignment the alignment marks should first be exposed on the JEOL. If the alignment marks are exposed with another tool, the alignment accuracy of the JEOL will be limited by the accuracy of the tool exposing the marks.
Two terms are used to describe alignment marks: global marks and chip marks. Global marks are typically larger marks placed at the outer edges of the wafer. These are used for coarse alignment and rotation adjustment. Chip marks are placed in the four corners of each chip and the written pattern is transformed to match the observed chip mark positions.
Global marks should be placed on the outer edges of the sample along the X and Y axis. A minimum of two global marks are allowed but four global marks per sample are standard and may give better alignment results.
Chip marks should be placed at the corners of each chip. In general, a chip usually covers no more than 20mm x 20mm. Each time a chip mark is used for an alignment it is essentially rendered unusable for future alignments. If multiple levels of alignment need to be performed, then multiple sets of chip marks need to be created. Each subsequent chip mark level should be offset toward the center of the chip by at least 100 microns in both the X and Y directions.
Standard global marks are crosses that are 2 millimeters long and 3 microns wide. Standard chip marks are crosses that are 60 microns long and 3 microns wide. Marks should be etched at least 1 micron into the substrate – 2 microns is ideal.
Metal liftoff can be used but it is not as reliable due to the chances of mark damage. Also, subsequent processing steps might cover the marks, compromising their ability to be recognized by the alignment system. If metal liftoff is used the metal should be Au or some other dense, high atomic number metal such as Pt or W. The thickness should be at least 50 nm.
Once the CAD layout is complete and a total process flow is developed, a “zero level exposure” is done on the JEOL. This is an exposure done to only expose the alignment marks. This exposure will include the alignment marks for the JEOL and may include marks for the steppers, contact aligners, and any other tool in the process flow. This exposure is developed and etched to at least 1 micron. This exposure will ensure the maximum possible overlay accuracy for all following process steps. Etching the alignment marks (as opposed to metal liftoff) will ensure that the likelihood of damage due to chemical or thermal processing is minimized. The UNAXIS 770 Bosch etcher is a good tool for performing the alignment mark etch in Si as it has high selectivity to resist.